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Senior Member Technical Staff
Responsibilities
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Determine logical verification strategy and approach for a particular ASIC,
SoC or any complex system
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Develop
behavioral models in
C++ and/or SystemC
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Write
the verification test plan
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Specify, develop, or enhance the verification environment, checkers and/or
bus functional models
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Develop
regressable, self-checking test suites
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Debug
the design and isolate failures
Requirements
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4+
years experience in logical verification of ASICs and systems
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Experience with C, C++ and SystemC
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Experience in Verilog and VHDL is a plus
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Experience in developing C/C++/SystemC based behavioral models on Linux,
Solaris and Windows platforms
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Demonstrated skills in applying reusability to the design and implementation
of Verification suites.
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Have
successfully defined, development, and used multiple verification
environments, using a variety of methodologies and techniques
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Experience in transferring verification environments and test suites to
others, and supporting their use
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Experience in writing test plans for ASICs / SoCs including embedded
processors
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Experience in implementing test suites and isolating failures
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Experience with embedded processors, DSPs, and/or standard busses is a plus
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Experience with Software Co-simulation is a plus
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Excellent software engineering skills, including programming style,
configuration and release management, and documentation
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Ability
to handle a team independently and identify the best solution among best
practices, based on personal experience
______________________________________________________Top
Member Technical Staff
Responsibilities
-
Develop
behavioral models in
C++ and/or SystemC
-
Specify, develop, or enhance the verification environment,
transactors/checkers and/or bus functional models
-
Develop
regressable, self-checking test suites
-
Debug
the design and isolate failures
Requirements
-
2+
years experience in logical verification of ASICs and systems
-
Experience with C, C++ and SystemC
-
Experience in Verilog and VHDL is a plus
-
Experience in developing C/C++/SystemC based behavioral models on Linux,
Solaris and Windows platforms
-
Experience in writing test plans for ASICs / SoCs including embedded
processors
-
Experience in implementing test suites and isolating failures
-
Experience with embedded processors, DSPs, and/or standard busses is a plus
-
Experience with Software Co-simulation is a plus
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Excellent software engineering skills, including programming style and
documentation
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Project Manager
Responsibilities
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Analysis and troubleshooting
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Design
& development of re-usable System level modeling IP components and
verification environments
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Builds,
leads and manages a team; handling recruitment, career development,
day-to-day tasks management, performance appraisals
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Customer interaction and presales activities
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Manage
project life cycle and bug free deliverables
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Strong
documentation skills
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Process
oriented
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Attention to detail
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Ability
to lead a team
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Meeting
deadlines
Requirements
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5+
years experience in managing projects in logical verification of ASICs, DSPs,
processor architectures and other systems
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Excellent knowledge of System level modeling and verification concepts
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Sound
knowledge of C++ and SystemC
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Excellent communication & interpersonal skills
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Exposure to SEI-CMM standards
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Strong
analytical skills
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Sound
knowledge of Linux based environments
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Ability to
meet deadlines
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